The insulated-gate static induction transistor has been used for high frequency amplifiers and integrated circuits which has the required high driving capability and the high operation speed. The insulated-gate static induction transistor was proposed by Jun-ichi Nishizawa who is one of the inventors of the present invention, and was published, for example, in JP,58-56270B, and JP,H3-00792B, etc. The insulated-gate static induction transistor and the insulated-gate transistor (MOS transistor, for example) are equivalent in that these have a source, a channel, and a drain, and currents flowing in them are controlled by a gate voltage, however their operation principles are different. That is, a potential barrier in the insulated-gate static induction transistor is formed by the gate voltage and the number of carriers traveling from the source to the drain are controlled by this potential barrier, on the contrary, in the insulated-gate transistor a semiconductor surface carrier density of an interface between a semiconductor surface and a gate insulator layer is changed by the gate voltage, and then the number of carriers traveling from the source to the drain is controlled by the gate voltage.
The insulated-gate static induction transistor is so designed that the effect of the drain electric field can have an influence on the source, and the current can be flown not only in the semiconductor-insulator interface but also inside of the substrate, so that it has such outstanding properties as an unsaturated current voltage characteristics, a high current driving capability, and a high speed performance etc.
However, the demand for an improvement of a data processing speed is more and more unlimited, and a further improvement in speed will be required for also in the insulated-gate static induction transistor. In order to increase the speed of the insulated-gate static induction transistor and the insulated-gate transistor, it is effective to shorten a channel length, the development of the insulated-gate transistor which has the cannel length of 1000 Å or less is progressing for a mass production, and also the channel length below the level of several 100 Å are being developed.
However, the depletion layer of the source and that of the drain approach or connect each other when a channel becomes shorter and shorter, it has such an intrinsic restriction in operation that currents in a short channel insulated-gate transistor become uncontrollable by the gate voltage. In the manufacturing method of an insulated-gate transistor using photolithography to form a short channel, a channel length of the insulated-gate transistor is determined by a light wavelength of photolithography, and then the shorter wavelength of the light source, i.e. an X-ray, is required to realize a channel length of 1000 Å or less. It is difficult to focus or bend an optical path of an X-ray, therefore an X-ray lithography apparatus is large and its cost is expensive, and also safety precautions to workers' to prevent an X-ray radiation exposure are indispensable.
As just described, a short channellization of an insulated-gate transistor is not making advances. Although an electron device based on an entirely new principle of an operation, for example, the device called a single electron transistor has been proposed, it does not go beyond the research. As will be understood from the foregoing description, a potential barrier is formed by the gate voltage and the number of carriers traveling from the source to the drain is controlled by it as the principle of operation in the insulated-gate static induction transistor, such a phenomenon does not occur that the depletion layer of the source and that of the drain connect each other, and hence the current becomes uncontrollable, and so it does not produce any restriction at all in the short channel insulated-gate static induction transistor.
And, when the molecular layer epitaxy method (see, for example, U.S. Pat. No. 5,294,286), which was invented by Dr. Jun-ichi Nishizawa et. al who is one of the inventors of the present invention, is used, a short channel can be grown with precision as accurate as single molecular layer without using the X-ray lithography apparatus.
Thus, the insulated-gate static induction transistor is highlighted as a next-generation ultra high-speed electron device.
Next, a prior art insulated-gate static induction transistor will be explained. FIG. 8 illustrates the manufacturing method and the structure of the prior art insulated-gate static induction transistor, and its manufacturing process is as follows. First, as shown in FIG. 8(a), an epitaxial layer 52 is grown as a channel on a semiconductor substrate 51, and then a projection portion 52 is formed by using anisotropic etching. As shown in FIG. 8(b), the masking is carried out using a field oxide film 53, and a gate oxide film 54 is formed in the portion of a device fabrication region.
Next as is shown in FIG. 8(c), the polycrystalline semiconductor as for a gate electrode 55 is deposited and etched to form a gate electrode on a sidewall of the projection region 52 by the anisotropic etching, and a drain 56 and a source 57 are formed by the ion implantation using a gate electrode 55 as a mask.
And as shown in FIG. 8(d), a passivation film 58 is deposited, holes are opened onto the passivation film 58 for electrodes, a drain electrode 56′ and a source electrode 57′ are formed, and finally an annealing process for impurity activation is carried out.
In the structure of the insulated-gate static induction transistor mentioned above, the high temperature processes for the activation of the ion implanted impurities and for the gate oxide layer formation are indispensable, then impurities are distributed during these high temperature processes, and especially the impurities of the drain 56 were diffused into the channel 52 to shorten the channel length. When a channel length of the device becomes as same as the diffusion length of impurities, it is varied by every impurity diffusion process, a problem has been associated as a consequence that an operation characteristics is changed for each transistor.
Although the height of the projection part 52 may be influenced to the length of a channel, the accuracy of the anisotropic etching can not correspond to the channel length of 1000 Å or less, and, for this reason, a problem has been encountered that the insulated-gate static induction transistor of a certain channel length cannot be manufactured with a sufficient accuracy and with a good reproducibility.
At the same time, in this structure of the insulated-gate static induction transistor as shown in FIG. 8(d), the gate electrode 55 and the gate oxide film 54 are contacted with not only the channel 52 but also the drain 56 and the source 57. For this reason, parasitic capacitances are generated among the gate electrode 55, the drain 56 and the source 57, so the problem has been encountered that an operation speed of the device is limited by these parasitic capacitances especially when a short channel is formed.
Considering the above described problems, the primary object of the present invention is to provide an ultra high-speed vertical type short channel insulated-gate static induction transistor with a uniform operating characteristics which has a short channel length of 1000 Å to 100 Å.
Furthermore, the second object of the present invention is to provide an ultra high-speed planar type short channel insulated-gate static induction transistor with a channel length from 1000 Å to 100 Å and with the parasitic capacitance as small as to the limit.
And, furthermore, the third object of the present invention is to provide their manufacturing methods of the same.